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-- NAND gate
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library ieee;
use ieee.std_logic_1164.all;

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entity NAND_ent is
port(
	x: in std_logic;
	y: in std_logic;
	z: out std_logic;
);
end NAND_ent;

------------------------------

architecture NAND_arch of NAND_ent is
begin
	process(x, y)
	begin
		if ((x='1') and (y='1')) then
			z <= '0'; 
		else
			z <= '1';
		end if;
	end process;
end NAND_arch;

architecture NAND_beh of NAND_ent is
begin
	z <= x nand y;
end NAND_beh;

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